Not Applicable.
Not Applicable.
The present invention relates to shared memory units and more particularly to a system for managing access to a shared memory by a plurality of independent data access devices.
As their name implies, application specific integrated circuits, or ASICs, are essentially integrated circuits implemented on a chip designed for a specific use or application. ASICs are used for numerous applications. For instance, ASICs are used for machine-to-machine communications for the space shuttle, for DVD processing, for advanced digital signal processing, for trans-oceanic cables, etc. Such special purpose processors can be embedded in essentially any equipment to enhance and control its functions.
Typically an ASIC includes one or more core processors, including digital signal processors (DSPs), memory and other functional devices on a single semiconductor chip. Having the devices on the same chip allows data to be easily and quickly transferred between the various devices on the chip. The memory used in ASICs may be shared memory, which allows the various core processors and other devices to work with the same sets of data or transfer data by writing and reading from the same memory addresses.
While the use of shared memory has a number of advantages, it may also slow down the overall system operation. Standard memory and bus protocols require that each device reading from or writing to a memory, i.e. masters, must request a transaction and then wait until the memory, i.e. the slave, has completed the transaction before requesting another transaction. In shared memory, this can cause delays because the memory can process only one request at a time and other devices may have priority. For example, if a digital signal processor (DSP) is one of the devices using the shared memory, it may be given the highest priority for access to the memory. For a single master accessing shared memory through a dedicated port, the memory may be provided with a request queue which allows the master to proceed with other operations while its memory transaction requests are pending in the queue.
Since there are a limited number of access ports for a shared memory unit, multiple cores, DSPs, and other independent access devices may need to share a single memory port. In this case, use of a queue causes a problem, because transaction requests from more than one master will be placed in the queue in the order in which received. However, when each transaction is completed there is no way for the multiple masters to know which one requested the transaction and should, for example, read the data being provided by the memory. If a queue is not used, then not only must the requesting master wait for completion of its request, but other master requests cannot be made until the pending transaction is completed.
It would be desirable to be able to use an input queue in a shared memory port and also allow multiple devices to share the same input port.
In accordance with the present invention, a system is provided for receiving memory transaction requests from a plurality of masters, coupling the requests to a port of a shared memory having an input queue, identifying each request with the requesting device and identifying each memory response with the proper requesting device. The system includes a request controller for receiving requests from the plurality of masters and selectively forwarding the requests to the shared memory. It also includes a first-in-first-out memory for storing an identifier of the source of each request coupled to the shared memory and for providing source identifier information to route each memory response to the master which made the request corresponding to the response.